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.05 Low Voltage Swing Terminated Logic (LVSTL05)standard by JEDEC Solid State Technology Association, 06/01/2019
JOINT IPC/JEDEC STANDARD FOR ACOUSTIC MICROSCOPY FOR NONHERMETRIC ENCAPSULATED ELECTRONIC COMPONENTSstandard by JEDEC Solid State Technology Association, 05/01/1999
BALL GRID ARRAY PINOUTS STANDARDIZED FOR 8-BIT LOGIC FUNCTIONSstandard by JEDEC Solid State Technology Association, 07/01/2001
RANGES AND CONDITIONS FOR SPECIFYING BETA FOR LOW POWER, AUDIO FREQUENCY TRANSISTORS FOR ENTERTAINMENT SERVICEstandard by JEDEC Solid State Technology Association, 01/01/1965
CONDITIONS FOR MEASUREMENT OF DIODE STATIC PARAMETERSstandard by JEDEC Solid State Technology Association, 12/01/1992
ADDENDUM No. 6 to JESD24 – THERMAL IMPEDANCE MEASUREMENTS FOR INSULATED GATE BIPOLAR TRANSISTORSAmendment by JEDEC Solid State Technology Association, 10/01/2001
STANDARD FOR DESCRIPTION OF 2.5 V CMOS LOGIC DEVICESstandard by JEDEC Solid State Technology Association, 11/01/1999
ADDENDUM No. 4 to JESD8 – CENTER-TAP-TERMINATED (CTT) INTERFACE LOW-LEVEL, HIGH-SPEED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITSstandard by JEDEC Solid State Technology Association, 11/01/1993
1.8 V HIGH-SPEED LVCMOS (HS_LVCMOS) INTERFACEstandard by JEDEC Solid State Technology Association, 03/01/2018
